RRAM structure at STI with Si-based selector

ABSTRACT

An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.

CROSS-REFERENCED APPLICATION

This application is a division of U.S. application Ser. No. 13/611,817 filed Sep. 12, 2012, entirety of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to semiconductor memories. The present disclosure is particularly applicable to nonvolatile resistive random access memories (RRAMs).

BACKGROUND

Present flash technologies have encountered significant challenges for scaling such as scaling of program/erase (P/E) voltage, speed, reliability, number of charges stored per floating gate and their variability. Attempts to solve such issues have included employing RRAMs due to their scalability, highly competitive speed, endurance, and retention properties. RRAMs have been placed within contacts, above contacts, between M2 and M3 layers, and above backend layers. Single transistor single resistor (1T1R) RRAMs, which are desirably bipolar and have a high access current, also have a large cell size of 8F² or higher and are not easily scalable. Single diode single resistor (1D1R) RRAMs, on the other hand, have a smaller cell size of 4F² or higher, and are easily scalable, but are unipolar and have a low access current. In addition, 1D1R RRAMs employ metal oxide diodes or organic diodes, which are compatible with back-end-of-line (BEOL) processes because of processing temperatures less than 400° C. However, the diodes of such materials are not tunable, have inferior diode performance (i.e., low forward current due to large band-gap), which leads to larger cell area and a high Vdd of 3 to 4.5 V, which is not compatible with low Vdd technology.

A need therefore exists for methodology enabling fabrication of RRAMs which have a small cell size, are easily scalable, have a high access current, and are bipolar, and the resulting product.

SUMMARY

An aspect of the present disclosure is a method of fabricating a compact RRAM using an embedded vertical bipolar junction transistor (BJT).

Another aspect of the present disclosure is a compact RRAM using an embedded vertical BJT.

Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.

According to the present disclosure, some technical effects may be achieved in part by a method including: defining a shallow trench isolation (STI) region in a substrate; implanting dopants in the substrate to form a well of a first polarity around and below a bottom portion of the STI region, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate; forming a hardmask on the active areas; removing a top portion of the STI region to form a cavity; forming an RRAM liner on side and bottom surfaces of the cavity; forming a top electrode in the cavity; removing a portion of the hardmask to form spacers on opposite sides of the cavity; and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.

Aspects of the present disclosure include the bottom surface of the cavity being above a top surface of the band of a second polarity. Further aspects include forming the active areas with a shallow implant and implanting the dopant of the second polarity in each active area using multiple energies. Other aspects include activating all of the dopants after implanting the dopant of the second polarity in each active area. Another aspect includes forming the hardmask of silicon nitride. An additional aspect includes forming the RRAM liner to a thickness of 3 nanometers (nm) to 900 nm. Further aspects include the RRAM liner including an oxide of a transition metal. Other aspects include the top electrode including a transition metal, titanium nitride (TiN), TiN/Ti, or polysilicon.

Another aspect of the present disclosure is a method including defining a shallow trench isolation (STI) region in a substrate; implanting dopants in the substrate to form a well of a first polarity around and below a bottom portion of the STI region, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate; forming a hardmask on the active areas; removing a top portion of the STI region to form a cavity; forming a sacrificial top electrode in the cavity; removing a portion of the hardmask to form spacers on opposite sides of the cavity; implanting a dopant of the second polarity in a portion of each active area remote from the cavity; removing the sacrificial top electrode; forming an RRAM liner on side and bottom surfaces of the cavity; and forming a top electrode in the cavity.

Aspects include the bottom surface of the cavity being above a top surface of the band of a second polarity. Additional aspects include forming the active areas with a shallow implant and implanting the dopant of the second polarity in each active area using multiple energies. Other aspects include activating all of the dopants prior to removing the sacrificial top electrode. Another aspect includes forming a protection layer over the active areas prior to removing the sacrificial top electrode. Further aspects include forming the hardmask of silicon nitride. Additional aspects include forming the RRAM liner of an oxide of a transition metal and to a thickness of 3 nm to 900 nm. Further aspects include the top electrode including a transition metal, titanium nitride (TiN), TiN/Ti, or polysilicon.

Another aspect of the present disclosure is a device including: a substrate; a well of a first polarity in the substrate; a shallow trench isolation (STI) region formed in the substrate extending partially into the well; a band of a second polarity in the substrate, over the well, at opposite sides of the STI region; an area of the first polarity in the substrate over the band at opposite sides of each STI region; an area of the second polarity in the substrate over the band adjacent each area of the first polarity, remote from the STI region; a recess in a top surface of a portion of the STI region; an RRAM liner on side and bottom surfaces of the recess; and a top electrode in the recess, wherein the bottom surface of the recess is above a top surface of the band.

Aspects include the RRAM liner including an oxide of a transition metal. Further aspects include a thickness of the RRAM liner being 3 nm to 900 nm. Other aspects include the top electrode including a transition metal, titanium nitride (TiN), TiN/Ti, or polysilicon.

Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

FIGS. 1A through 4A and 1B through 4B schematically illustrate top views and cross-sectional views, respectively, of a process flow, in accordance with an exemplary embodiment;

FIGS. 5A through 7A and 5B through 7B schematically illustrate top views and cross-sectional views, respectively, of a process flow, in accordance with another exemplary embodiment; and

FIGS. 8A through 8C schematically illustrate a layout scheme for the structures formed by the processes of the first and second embodiments.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”

The present disclosure addresses and solves the current problems of difficult scalability, low access current, large cell size and/or unipolarity attendant upon fabricating a 1T1R or a 1D1R RRAM. In accordance with embodiments of the present disclosure, a compact RRAM is formed using an embedded vertical BJT.

Methodology in accordance with embodiments of the present disclosure includes defining a shallow trench isolation (STI) region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below a bottom portion of the STI region, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate. A hardmask is then formed on the active areas, a top portion of the STI region is removed to form a cavity, an RRAM liner is formed on side and bottom surfaces of the cavity, a top electrode is formed in the cavity, a portion of the hardmask is removed to form spacers on opposite sides of the cavity, and a dopant of the second polarity is implanted in a portion of each active area remote from the cavity.

Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

FIGS. 1A through 4A schematically illustrate a top view of a process flow in accordance with an exemplary embodiment, and FIGS. 1B through 4B schematically illustrate corresponding cross-sectional views of the process flow. Adverting to FIGS. 1A and 1B, STI regions 103 are defined on a p-type substrate 101. The STI regions may be formed to a depth of 100 nanometer (nm) to 1000 nm and to a width of 50 nm to 200 nm, depending on the technology node, and may be formed, for example, of silicon dioxide (SiO₂), silicon nitride (Si₃N₄), or silicon oxynitride (SiON). N-wells 105 are formed around the bottom portions of the STI regions by implanting N-type dopants (e.g., phosphorus (P), arsenic (As), etc.) at a dosage of 1E12 to 9E13 with an energy of 10 keV to 900 keV depending on the STI depth. Next, a p-band 107 is formed over the n-wells on opposite sides of the STI region by implanting P-type dopant (e.g., boron (B), boron difluoride (BF₂), indium (In), etc.) at a dosage of 1E12 to 9E13 and with an energy of 10 keV to 100 keV. Then, a shallow n-type implant is performed over the p-band on opposite sides of the STI region by implanting N-type dopants (e.g., P, As, etc.) at a dosage of 1E12 to 9E13 and with an energy of 1 keV to 10 keV, forming n-type active area 109.

As illustrated in FIGS. 2A and 2B, a hardmask, such as silicon nitride (SiN) 201 is deposited over the entire substrate. Then, using a mask with openings 203, the portion of hardmask 201 over STI regions 103 and a top portion of STI regions 103 are removed, such as by etching, forming cavities 205. After the etching is complete, the bottom surface 207 of cavities 205 must be above a top surface 209 of p-band 107, to prevent short-circuit paths to other terminals.

An RRAM liner 301 is then conformally deposited in cavities 205, as illustrated in FIGS. 3A and 3B. RRAM liner 301 may be formed of titanium oxide (TiO_(x)), nickel oxide (NiO_(x)), hafnium oxide (HfO_(x)), tungsten oxide (WO_(x)), tantalum oxide (TaO_(x)), vanadium oxide (VO_(x)), and copper oxide (CuO_(x)). The RRAM liner 301 may be formed to a thickness of a few nm to hundreds of nm. The remainder of each cavity 205 is then filled with a top electrode 303, followed by an etch-back or chemical mechanical polishing (CMP). Top electrode 303 may be formed of a material such as tungsten (W), platinum (Pt), titanium nitride (TiN), TiN/titanium (Ti), ruthenium (Ru), nickel (Ni), or polysilicon.

Adverting to FIGS. 4A and 4B, hardmask 201 is etched to form spacers 401 on opposite sides of top electrode 303. Then, multiple implantation steps are performed, implanting, for example, P-type dopant (e.g., B, BF₂, In, etc.), with different energies ranging from between sub keV (<1 keV) and 1 keV to between 2 keV and 10 keV, depending on the dopant used, to establish a desired implant profile for p-type regions 403. Once the implantations are complete, the dopants may be activated by heating to a temperature of 900° C. to 1100° C. for 1 millisecond (ms) to less than 5 seconds. Alternatively, a laser anneal may be performed to activate the dopants. Nickel silicide (NiSi) is then formed on p-type regions 403, and back-end-of line (BEOL) processing may continue.

FIGS. 5A through 7A schematically illustrate a top view of a process flow in accordance with another exemplary embodiment, in which a gate last approach is utilized, and FIGS. 5B through 7B schematically illustrate corresponding cross-sectional views of the process flow. The process begins the same as the first embodiment, through the formation of cavities 205 by removing both the portion of hardmask 201 over STI regions 103 and also a top portion of STI regions 103, such as by etching. Adverting to FIGS. 5A and 5B, cavities 205 are filled with a sacrificial top electrode 501, formed, for example by depositing polysilicon or amorphous silicon (a-Si).

As illustrated in FIGS. 6A and 6B, hardmask 201 is etched to form spacers 601 on opposite sides of sacrificial top electrode 501. Then, multiple implantation steps are performed, implanting, P-type dopant (e.g., B, BF₂, In, etc.), with different energies ranging from between sub keV (<1 keV) and 1 keV to between 2 keV and 10 keV, depending on the dopant used, to establish a desired implant profile for p-type regions 603. Once the implantations are complete, the dopants may be activated by heating to a temperature of 900° C. to 1100° C. for 1 millisecond (ms) to less than 5 seconds. Alternatively, a laser anneal may be performed to activate the dopants.

A protection layer (not shown for illustrative convenience), formed for example of SiO2 or SiON, is then deposited over p-type regions 603 (the active regions), and sacrificial top electrode 501 is removed. As illustrated in FIGS. 7A and 7B, an RRAM liner 701 is then conformally deposited in cavities 205. RRAM liner 301 may be formed of titanium oxide (TiO_(x)), nickel oxide (NiO_(x)), hafnium oxide (HfO_(x)), tungsten oxide (WO_(x), tantalum oxide (TaO_(x)), vanadium oxide (VO_(x)), and copper oxide (CuO_(x)). The RRAM liner 701 may be formed to a thickness of a few nm to hundreds of nm. The remainder of each cavity 205 is then filled with a top electrode 703, followed by an etch-back or chemical mechanical polishing (CMP). Top electrode 703 may be formed of a material such as tungsten (W), platinum (Pt), titanium nitride (TiN), TiN/titanium (Ti), ruthenium (Ru), nickel (Ni), or polysilicon. Nickel silicide (NiSi) is then formed on p-type regions 603, and back-end-of line (BEOL) processing may continue.

Adverting to FIGS. 8A through 8C, a layout of RRAMs of FIGS. 4A and 4B is illustrated. As shown in FIGS. 8A through 8C, a first bit line 801 is connected to the p-type region 403 on one side of the STI region, and a second bit line 803 is connected to the p-type region 403 on the other side of the STI region. A first word line 805 is connected to a first column of top electrodes 303, and a second word line 809 is connected to a second column of top electrodes 303. A select line 807 is formed in n-wells 105.

Read, set, and reset operations of the RRAM at the STI can be achieved by passing current through selected BJTs and RRAM. For example, for a read operation, a high read voltage may be applied to the selected word line, a select read voltage may be applied to the selected bit line, and a low voltage may be applied to the select line. Similarly, for a set operation, a high set voltage may be applied to the selected word line, a select set voltage may be applied to the selected bit line, and a low voltage may be applied to the select line. For reset operations, a select reset voltage may be applied to the selected bit line. Then, for a unipolar reset operation, a high reset voltage may be applied to the selected word line and a low voltage may be applied to the select line, whereas for a bipolar operation, a low reset voltage may be applied to the selected word line and a high voltage may be applied to the select line. In addition, for forming operations, a high forming voltage may be applied to the selected word line, a select forming voltage may be applied to the selected bit line, and a low voltage may be applied to the select line. For all forming, read, set, and reset operations, unselected word lines and unselected bit lines may be floating.

The embodiments of the present disclosure can achieve several technical effects, such as direct access to the RRAM with a high access current through a silicon-based selector (the vertical BJT), cell performance and scalability being independent from the gate oxide and gate length, thereby reducing cell size and increasing scalability, bidirectionality of the RRAM without increasing cell size, and compatibility with both gate first and gate last approaches. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, digital cameras, or in any memory product. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices.

In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein. 

What is claimed is:
 1. A device comprising: a substrate; a well of a first polarity in the substrate; a shallow trench isolation (STI) region formed in the substrate extending partially into the well; bands of a second polarity in the substrate, over the well, at opposite sides of the STI region; an area of the first polarity at a top surface of the substrate over each band; an area of the second polarity in the substrate over each band, adjacent each area of the first polarity and remote from the STI region; a recess in a top portion of the STI region, wherein a bottom surface of the recess is above a top surface of the band; a resistive random access memory (RRAM) liner on side and bottom surfaces of the recess; and a top electrode in the recess.
 2. The device according to claim 1, wherein the RRAM liner comprises an oxide of a transition metal.
 3. The device according to claim 1, wherein a thickness of the RRAM liner is 3 nm to 900 nm.
 4. The device according to claim 1, wherein the top electrode comprises a transition metal, titanium nitride (TiN), TiN/Ti, or polysilicon.
 5. The device according to claim 1, further comprising silicon nitride (SiN) spacers at opposite sides of the top electrode.
 6. The device according to claim 1, wherein the STI region has a depth of 100 to 1000 nm.
 7. The device according to claim 1, wherein the STI region comprises silicon dioxide (SiO₂), silicon nitride (Si₃N₄) or silicon oxynitride (SiON).
 8. The device according to claim 1, wherein the well is implanted with phosphorus (P) or arsenic (As).
 9. The device according to claim 8, wherein the band of a second polarity is implanted with boron (B), boron difluoride (BF₂), or indium (In).
 10. A device comprising: a substrate; plural wells of a first polarity in the substrate; shallow trench isolation (STI) regions formed in the substrate, parallel to and separated from each other, each STI region extending partially into a different one of the plural wells; bands of a second polarity in the substrate, over the wells, at opposite sides of each STI region; first and second areas of the first polarity at a top surface of the substrate over each band, at opposite sides of each STI region; first and second areas of the second polarity in the substrate over each band, adjacent the first and second areas, respectively, of the first polarity and remote from the corresponding STI region; a recess in a top portion of each STI region, wherein a bottom surface of each recess is above a top surface of each band; a resistive random access memory (RRAM) liner on side and bottom surfaces of each recess; and a top electrode in each recess.
 11. The device according to claim 10, wherein each RRAM liner comprises an oxide of a transition metal.
 12. The device according to claim 10, wherein a thickness of each RRAM liner is 3 nm to 900 nm.
 13. The device according to claim 10, wherein the top electrode comprises a transition metal, titanium nitride (TiN), TiN/Ti, or polysilicon.
 14. The device according to claim 10, further comprising silicon nitride (SiN) spacers at opposite sides of each top electrode.
 15. The device according to claim 10, wherein each STI region has a depth of 100 to 1000 nm.
 16. The device according to claim 10, wherein each STI region comprises silicon dioxide (SiO₂), silicon nitride (Si₃N₄) or silicon oxynitride (SiON).
 17. The device according to claim 10, wherein each well is implanted with phosphorus (P) or arsenic (As).
 18. The device according to claim 17, wherein each band of a second polarity is implanted with boron (B), boron difluoride (BF₂), or indium (In).
 19. The device according to claim 10, further comprising: first and second bit lines connected to the first and second areas of second polarity, respectively; first and second word lines connected to first and second columns of top electrodes, respectively; and a select line formed in the wells.
 20. A device comprising: a substrate; plural wells of a first polarity in the substrate; shallow trench isolation (STI) regions formed in the substrate, parallel to and separated from each other, each STI region extending partially into a different one of the plural wells; bands of a second polarity in the substrate, over the wells, at opposite sides of each STI region; first and second areas of the first polarity at a top surface of the substrate over each band, at opposite sides of each STI region; first and second areas of the second polarity in the substrate over each band, adjacent the first and second areas of the first polarity, respectively, and remote from the corresponding STI region; a recess in a top portion of each STI region, wherein a bottom surface of each recess is above a top surface of each band; a resistive random access memory (RRAM) liner comprising an oxide of a transition metal having a thickness of 3 nm to 900 nm on side and bottom surfaces of each recess; a top electrode comprising a transition metal, titanium nitride (TiN), TiN/Ti, or polysilicon in each recess; silicon nitride (SiN) spacers at opposite sides of each top electrode; first and second bit lines connected to the first and second areas of second polarity, respectively; first and second word lines connected to first and second columns of top electrodes, respectively; and a select line formed in the wells. 